The emergence of services including Voice over Internet Protocol (VoIP), Internet Protocol Television (IPTV), The 3rd Generation Telecommunication (3G) technology, the Long Term Evolution (LTE) technology and the metro Ethernet Private line along with the rapid development of new services taking Internet Protocol (IP) as the core leads to not only a continue increase in demands for bandwidth but also a more meticulous user classification and a more effective and reliable data service management. The grouping of services urges the gradual evolution from access network, bearer network and core network device to the next generation network which takes packet switching as the core. The capability of a data chip in forwarding and processing various service messages, as an important function of the data chip, is continuously required to be improved and becomes more and more functionally complicated.
One of the major functions of the great number of access networks, bearer networks and core network devices existing in a communication network is to forward and process service messages, for example, an Optical Line Terminal (OLT) and an Optical Network Unit (ONU) in a Passive Optical Network (PON) and an Ethernet switch, a Broadband Remote Access Server (BRAS), a router and the like in a data communication network all need to forward and process various kinds of messages.
For a certain type of devices, as the earlier service processing requirement is relatively monotonous, the conventional message modification function generally aims at a part of fields in a message, for example, the Virtual Local Area Network (VLAN) priority mark in an Ethernet message head, a label tag in a Multi-Protocol Label Switching (MPLS) message or a head of an IP message and the like. However, as the demands for services increase continuously, to modify each independent field of different kinds of messages, in logic structure, it is designed to modify each field in a message in a parallel manner and modify each field using an independent logical processing unit.
Thus, it can be known that this existing design scheme brings problems in two aspects: aspect 1, as the increase in the functions of a chip is accompanied by the significant increase of the area and the power consumption of the chip, to balance the functions, the performance ad the cost of the chip, it is needed to decrease some functions of the chip, which is not a desirable choice for the designer of the chip; aspect 2: in order to meet some new demands or cope with changes in demands, a larger and larger amount of work needs to be done to add or modify logical codes on the basis of existing processing logic, and the post-maintenance of the codes becomes more and more complicated, leading to a great increase in both code maintenance time and code maintenance cost